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74HCT9046A
PLL with band gap controlled VCO
Rev. 06 -- 15 September 2009 Product data sheet
1. General description
The 74HCT9046A is a high-speed Si-gate CMOS device. It is specified in compliance with JEDEC standard no 7A.
2. Features
I I I I I Operation power supply voltage range from 4.5 V to 5.5 V Low power consumption Inhibit control for ON/OFF keying and for low standby power consumption center frequency up to 17 MHz (typical) at VCC = 5.5 V Choice of two phase comparators: N PC1: EXCLUSIVE-OR N PC2: Edge-triggered JK flip-flop No dead zone of PC2 Charge pump output on PC2, whose current is set by an external resistor Rbias center frequency tolerance 10 % Excellent Voltage Controlled Oscillator (VCO) linearity Low frequency drift with supply voltage and temperature variations On-chip band gap reference Glitch free operation of VCO, even at very low frequencies Zero voltage offset due to operational amplifier buffering ESD protection: N HBM JESD22-A114F exceeds 2000 V N MM JESD22-A115-A exceeds 200 V
I I I I I I I I I
NXP Semiconductors
74HCT9046A
PLL with band gap controlled VCO
3. Applications
I FM modulation and demodulation where a small center frequency tolerance is essential I Frequency synthesis and multiplication where a low jitter is required (e.g. video picture-in-picture) I Frequency discrimination I Tone decoding I Data synchronization and conditioning I Voltage-to-frequency conversion I Motor-speed control
4. Ordering information
Table 1. Ordering information Package Temperature range Name 74HCT9046AN 74HCT9046AD 74HCT9046APW -40 C to +125 C -40 C to +125 C -40 C to +125 C DIP16 SO16 TSSOP16 Description plastic dual in-line package; 16 leads (300 mil) plastic small outline package; 16 leads; body width 3.9 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm Version SOT38-4 SOT109-1 SOT403-1 Type number
74HCT9046A_6
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Product data sheet
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74HCT9046A
PLL with band gap controlled VCO
5. Block diagram
fout
C1
fin C1A 6 C1B 7 VCO_OUT COMP_IN SIG_IN 4 3 14
VCC
16
9046A
R2 12 PHASE COMPARATOR 1 PC1_OUT/ 2 PCP_OUT
R3
R2
VCO R1 11
R1
PHASE COMPARATOR 2
13 PC2_OUT 15 RB
Rbias R4 C2
5 INH
10
9
8 GND
1 GND
mbd040
DEM_OUT VCO_IN
Rs
Fig 1.
Block diagram
6. Functional diagram
3 14 15
COMP_IN SIG_IN RB
PC1_OUT/ PCP_OUT
2
PC2_OUT
PLL 9046A 3 14 6
COMP_IN SIG_IN C1A C1B R1 R2 RB VCO_IN INH
mbd039
13
PC1_OUT/ PCP_OUT PC2_OUT
2 13
6 7 11 12 9 5
C1A C1B R1 R2 VCO_IN INH
mbd038
7
VCO_OUT
4
11 12 15
VCO
DEM_OUT
DEM_OUT VCO_OUT
10 4
10
9 5
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
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Product data sheet
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Product data sheet Rev. 06 -- 15 September 2009 4 of 43
74HCT9046A_6
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C1
fout 7 4 COMP_IN 3
fin 14 SIG_IN PC1
6 C1A
C1B VCO_OUT
Vref2 12
R2
PC1_OUT/ PCP_OUT 2
R2 VCO
R3
Vref1 11
R1
logic 1
D CP
Q
up
PCP
R1
Q RD
logic 1 10 DEM_OUT
RS
D CP
Q down CHARGE PUMP
PC2_OUT 13
(1) R3' R4 C2
Vref1
Vref2
Q RD
RB 15
Rbias
BAND GAP
Vref2
VCO_IN 9
INH 5
PLL with band gap controlled VCO
(1)
R3' = Rbias /17
mbd102
Fig 4.
Logic diagram
74HCT9046A
(c) NXP B.V. 2009. All rights reserved.
NXP Semiconductors
74HCT9046A
PLL with band gap controlled VCO
7. Pinning information
7.1 Pinning
74HCT9046A
GND PC1_OUT/ PCP_OUT COMP_IN VCO_OUT INH C1A C1B GND
1 2 3 4 5 6 7 8
001aae500
16 VCC 15 RB 14 SIG_IN 13 PC2_OUT 12 R2 11 R1 10 DEM_OUT 9 VCO_IN
Fig 5.
Pin configuration
7.2 Pin description
Table 2. Symbol GND PC1_OUT/PCP_OUT COMP_IN VCO_OUT INH C1A C1B GND VCO_IN DEM_OUT R1 R2 PC2_OUT SIG_IN RB VCC Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Description ground (0 V) of phase comparators phase comparator 1 output or phase comparator pulse output comparator input VCO output inhibit input capacitor C1 connection A capacitor C1 connection B ground (0 V) VCO VCO input demodulator output resistor R1 connection resistor R2 connection phase comparator 2 output; current source adjustable with Rbias signal input bias resistor (Rbias) connection supply voltage
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74HCT9046A
PLL with band gap controlled VCO
8. Functional description
The 74HCT9046A is a phase-locked-loop circuit that comprises a linear VCO and two different phase comparators (PC1 and PC2) with a common signal input amplifier and a common comparator input, see Figure 1. The signal input can be directly coupled to large voltage signals (CMOS level), or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the 74HCT9046A forms a second-order loop PLL. The principle of this phase-locked-loop is based on the familiar 74HCT4046A. However extra features are built-in, allowing very high-performance phase-locked-loop applications. This is done, at the expense of PC3, which is skipped in this 74HCT9046A. The PC2 is equipped with a current source output stage here. Further a band gap is applied for all internal references, allowing a small center frequency tolerance. The details are summed up in Section 8.1. If one is familiar with the 74HCT4046A already, it will do to read this section only.
8.1 Differences with respect to the familiar 74HCT4046A * A center frequency tolerance of maximum 10 %. * The on board band gap sets the internal references resulting in a minimal frequency
shift at supply voltage variations and temperature variations.
* The value of the frequency offset is determined by an internal reference voltage of
2.5 V instead of VCC - 0.7 V; In this way the offset frequency will not shift over the supply voltage range.
* A current switch charge pump output on pin PC2_OUT allows a virtually ideal
performance of PC2; The gain of PC2 is independent of the voltage across the low-pass filter; Further a passive low-pass filter in the loop achieves an active performance. The influence of the parasitic capacitance of the PC2 output plays no role here, resulting in a true correspondence of the output correction pulse and the phase difference even up to phase differences as small as a few nanoseconds.
* Because of its linear performance without dead zone, higher impedance values for the
filter, hence lower C-values, can be chosen; correct operation will not be influenced by parasitic capacitances as in case of the voltage source output using the 74HCT4046A.
* No PC3 on pin RB but instead a resistor connected to GND, which sets the
load/unload currents of the charge pump (PC2).
* Extra GND pin 1 to allow an excellent FM demodulator performance even at 10 MHz
and higher.
* Combined function of pin PC1_OUT/PCP_OUT. If pin RB is connected to VCC (no
bias resistor Rbias) pin PC1_OUT/PCP_OUT has its familiar function viz. output of PC1. If at pin RB a resistor (Rbias) is connected to GND it is assumed that PC2 has been chosen as phase comparator. Connection of Rbias is sensed by internal circuitry and this changes the function of pin PC1_OUT/PCP_OUT into a lock detect output (PCP_OUT) with the same characteristics as PCP_OUT of pin 1 of the 74HCT4046A.
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Product data sheet
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74HCT9046A
PLL with band gap controlled VCO
* The inhibit function differs. For the 74HCT4046A a HIGH-level at the inhibit input
(pin INH) disables the VCO and demodulator, while a LOW-level turns both on. For the 74HCT9046A a HIGH-level on the inhibit input disables the whole circuit to minimize standby power consumption.
8.2 VCO
The VCO requires one external capacitor C1 (between pins C1A and C1B) and one external resistor R1 (between pins R1 and GND) or two external resistors R1 and R2 (between pins R1 and GND, and R2 and GND). Resistor R1 and capacitor C1 determine the frequency range of the VCO. Resistor R2 enables the VCO to have a frequency offset if required (see Figure 4). The high input impedance of the VCO simplifies the design of the low-pass filters by giving the designer a wide choice of resistor/capacitor ranges. In order not to load the low-pass filter, a demodulator output of the VCO input voltage is provided at pin DEM_OUT. The DEM_OUT voltage equals that of the VCO input. If DEM_OUT is used, a series resistor (Rs) should be connected from pin DEM_OUT to GND; if unused, DEM_OUT should be left open. The VCO output (pin VCO_OUT) can be connected directly to the comparator input (pin COMP_IN), or connected via a frequency divider. The output signal has a duty cycle of 50 % (maximum expected deviation 1 %), if the VCO input is held at a constant DC level. A LOW-level at the inhibit input (pin INH) enables the VCO and demodulator, while a HIGH-level turns both off to minimize standby power consumption.
8.3 Phase comparators
The signal input (pin SIG_IN) can be directly coupled to the self-biasing amplifier at pin SIG_IN, provided that the signal swing is between the standard HC family input logic levels. Capacitive coupling is required for signals with smaller swings.
8.3.1 Phase Comparator 1 (PC1)
This circuit is an EXCLUSIVE-OR network. The signal and comparator input frequencies (fi) must have a 50 % duty cycle to obtain the maximum locking range. The transfer characteristic of PC1, assuming ripple (fr = 2fi) is suppressed, is: V CC V DEM _OUT = ---------- ( SIG_IN - COMP_IN ) where: VDEM_OUT is the demodulator output at pin DEM_OUT VDEM_OUT = VPC1_OUT (via low-pass) V CC The phase comparator gain is: K p = ---------- ( V r ) The average output voltage from PC1, fed to the VCO input via the low-pass filter and seen at the demodulator output at pin DEM_OUT (VDEM_OUT), is the resultant of the phase differences of signals (SIG_IN) and the comparator input (COMP_IN) as shown in Figure 6. The average of VDEM_OUT is equal to 0.5VCC when there is no signal or noise at SIG_IN and with this input the VCO oscillates at the center frequency (f0). Typical
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74HCT9046A
PLL with band gap controlled VCO
waveforms for the PC1 loop locked at f0 are shown in Figure 7. This figure also shows the actual waveforms across the VCO capacitor at pins C1A and C1B (VC1A and VC1B) to show the relation between these ramps and the VCO_OUT voltage. The frequency capture range (2f0) is defined as the frequency range of input signals on which the PLL will lock if it was initially out-of-lock. The frequency lock range (2fL) is defined as the frequency range of the input signals on which the loop will stay locked if it was initially in lock. The capture range is smaller or equal to the lock range. With PC1, the capture range depends on the low-pass filter characteristics and can be made as large as the lock range. This configuration remains locked even with very noisy input signals. Typical behavior of this type of phase comparator is that it may lock to input frequencies close to the harmonics of the VCO center frequency.
VCC VDEM_OUT(AV)
mbd101
0.5VCC
0
0o
90 o
PC_IN
180 o
V CC V DEM _OUT = V PCI _OUT = ---------- SIG_IN - COMP_IN PC_IN = ( SIG_IN - COMP_IN ) Fig 6. Phase comparator 1; average output voltage as a function of input phase difference
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Product data sheet
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74HCT9046A
PLL with band gap controlled VCO
SIGN_IN
COMP_IN VCO_OUT
PC1_OUT
VCC VCO_IN GND
VC1A
C1A
VC1B
C1B
mbd100
Fig 7.
Typical waveforms for PLL using phase comparator 1; loop-locked at f0
8.3.2 Phase Comparator 2 (PC2)
This is a positive edge-triggered phase and frequency detector. When the PLL is using this comparator, the loop is controlled by positive signal transitions and the duty cycles of SIG_IN and COMP_IN are not important. PC2 comprises two D-type flip-flops, control gating and a 3-state output stage with sink and source transistors acting as current sources, henceforth called charge pump output of PC2. The circuit functions as an up-down counter (see Figure 4) where SIG_IN causes an up-count and COMP_IN a down count. The current switch charge pump output allows a virtually ideal performance of PC2, due to appliance of some pulse overlap of the up and down signals, see Figure 8a. The pump current Icp is independent from the supply voltage and is set by the internal band gap reference of 2.5 V. 2.5 I cp = 17 x ----------- ( A ) R bias Where Rbias is the external bias resistor between pin RB and ground. The current and voltage transfer function of PC2 are shown in Figure 9. The phase comparator gain is: I cp K P = --------- ( A r ) 2
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Product data sheet
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74HCT9046A
PLL with band gap controlled VCO
V up
CC
Icp PC2_OUT Icp
C2
VCC
up
R3' Icp
down
PC2_OUT VC2_OUT
C2
= PC_IN
pulse overlap of approximately 15 ns
mbd046
down
mbd099
a. At every , even at zero both switches are closed simultaneously for a short period (typically 15 ns). Fig 8. The current switch charge pump output of PC2
b. Comparable voltage-controlled switch
+Icp
VCC
VDEM_OUT(AV) 0 0.5VCC
Icp x R
-Icp -2 0 PC_IN +2 0 -2
0
001aak442
PC_IN
+2
001aak443
a. Current transfer
b. Voltage transfer. This transfer can be observed at PC2_OUT by connecting a resistor (R = 10 k) between PC2_OUT and 0.5VCC. 5 V DEM _OUT = V PC2_OUT = ----- PC_IN - 4 PC_IN = ( SIG_IN - COMP_IN )
I cp pump current --------- PC_IN 2
Fig 9.
Phase comparator 2 current and voltage transfer characteristics
When the frequencies of SIG_IN and COMP_IN are equal but the phase of SIG_IN leads that of COMP_IN, the up output driver at PC2_OUT is held `ON' for a time corresponding to the phase difference (PC_IN). When the phase of SIG_IN lags that of COMP_IN, the down or sink driver is held `ON'.
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74HCT9046A
PLL with band gap controlled VCO
When the frequency of SIG_IN is higher than that of COMP_IN, the source output driver is held `ON' for most of the input signal cycle time and for the remainder of the cycle time both drivers are `OFF' (3-state). If the SIG_IN frequency is lower than the COMP_IN frequency, then it is the sink driver that is held `ON' for most of the cycle. Subsequently the voltage at the capacitor (C2) of the low-pass filter connected to PC2_OUT varies until the signal and comparator inputs are equal in both phase and frequency. At this stable point the voltage on C2 remains constant as the PC2 output is in 3-state and the VCO input at pin 9 is a high-impedance. Also in this condition the signal at the phase comparator pulse output (PCP_OUT) has a minimum output pulse width equal to the overlap time, so can be used for indicating a locked condition. Thus for PC2 no phase difference exists between SIG_IN and COMP_IN over the full frequency range of the VCO. Moreover, the power dissipation due to the low-pass filter is reduced because both output drivers are OFF for most of the signal input cycle. It should be noted that the PLL lock range for this type of phase comparator is equal to the capture range and is independent of the low-pass filter. With no signal present at SIG_IN the VCO adjust, via PC2, to its lowest frequency. By using current sources as charge pump output on PC2, the dead zone or backlash time could be reduced to zero. Also, the pulse widening due to the parasitic output capacitance plays no role here. This enables a linear transfer function, even in the vicinity of the zero crossing. The differences between a voltage switch charge pump and a current switch charge pump are shown in Figure 11.
SIG_IN
COMP_IN VCO_OUT
UP PC_IN DOWN
15 ns typical
CURRENT AT PC2_OUT high-impedance OFF-state, (zero current) PC2_OUT/VCO_IN
PCP_OUT
mbd047
The pulse overlap of the up and down signals (typically 15 ns).
Fig 10. Timing diagram for PC2
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74HCT9046A
PLL with band gap controlled VCO
2.75
2.75
VCO_IN
VCO_IN
(1)
2.50
(1)
2.50
(2)
2.25 -25
0
phase error (ns)
25
2.25 -25
0
phase error (ns)
25
001aak444
001aak445
(1) Due to parasitic capacitance on PC2_OUT. (2) Backlash time (dead zone).
a. Response with traditional voltage-switch charge-pump PC2_OUT (74HCT4046A).
b. Response with current switch charge-pump PC2_OUT as applied in the 74HCT9046A.
Fig 11. The response of a locked-loop in the vicinity of the zero crossing of the phase error
The design of the low-pass filter is somewhat different when using current sources. The external resistor R3 is no longer present when using PC2 as phase comparator. The current source is set by Rbias. A simple capacitor behaves as an ideal integrator now, because the capacitor is charged by a constant current. The transfer function of the voltage switch charge pump may be used. In fact it is even more valid, because the transfer function is no longer restricted for small changes only. Further the current is independent from both the supply voltage and the voltage across the filter. For one that is familiar with the low-pass filter design of the 74HCT4046A a relation may show how Rbias relates with a fictive series resistance, called R3'. This relation can be derived by assuming first that a voltage controlled switch PC2 of the 74HCT4046A is connected to the filter capacitance C2 via this fictive R3' (see Figure 8b). Then during the PC2 output pulse the charge current equals: V CC - V C2 ( 0 ) I cp = -------------------------------R3' 2.5 With the initial voltage VC2(0) at: 0.5VCC = 2.5 V, I cp = ------R3' As shown before the charge current of the current switch of the 74HCT9046A is: 2.5 I cp = 17 x ----------R bias Hence: R bias R3` = ----------- ( ) 17
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Product data sheet
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74HCT9046A
PLL with band gap controlled VCO
Using this equivalent resistance R3' for the filter design the voltage can now be expressed as a transfer function of PC2; assuming ripple (fr = fi) is suppressed, as: 5 K PC2 = ----- ( V r ) 4 Again this illustrates the supply voltage independent behavior of PC2.
8.4 Loop filter component selection
Examples of PC2 combined with a passive filter are shown in Figure 12 and 13. Figure 12 shows that PC2 with only a C2 filter behaves as a high-gain filter. For stability the damped version of Figure 13 with series resistance R4 is preferred. Practical design values for Rbias are between 25 k and 250 k with R3' = 1.5 k to 15 k for the filter design. Higher values for R3' require lower values for the filter capacitance which is very advantageous at low values of the loop natural frequency n.
A
Icp Icp 17
Rbias
F(j)
INPUT
C2
OUTPUT
-1/A1
1/ A
001aak449
1
001aak450
001aak451
a. Simple loop filter for PC2 without damping
b. Amplitude characteristic
c. Pole zero diagram
A = DC gain limit, due to leakage
R bias 1 = ----------- x C2 = R3' x C2 17
1 1 F ( j ) = ---------------------------- ----------1 A + j 1 j 1
Fig 12. Simple loop filter for PC2 without damping
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Product data sheet
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74HCT9046A
PLL with band gap controlled VCO
A
Icp Icp 17
R4 Rbias
F(j)
INPUT
C2
OUTPUT
m
O -1/2
1/A
1
1/ A
001aak446
1
1 / A2
001aak447 001aak448
a. Simple loop filter for PC2 with damping
b. Amplitude characteristic
c. Pole zero diagram
A = DC gain limit, due to leakage
R bias 1 = ----------- x C2 = R3` x C2 17 2 = R4 x C2
1 + j 2 F ( j ) = ---------------------------1 A + j 1
Fig 13. Simple loop filter for PC2 with damping
9. Limiting values
Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK IOK IO ICC IGND Tstg Ptot Parameter supply voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation DIP16 SO16 and TSSOP16
[1] [2] For DIP16 packages: above 70 C the value of Ptot derates linearly with 12 mW/K. For SO16 and TSSOP16 packages: above 70 C the value of Ptot derates linearly with 8 mW/K.
Conditions VI < -0.5 V or VI > VCC + 0.5 V VO < -0.5 V or VO > VCC + 0.5 V -0.5 V < VO < VCC + 0.5 V
Min -0.5 -50 -65
Max +7 20 20 25 +50 +150 750 500
Unit V mA mA mA mA mA C mW mW
Tamb = -40 C to +125 C
[1] [2]
-
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74HCT9046A
PLL with band gap controlled VCO
10. Recommended operating conditions
Table 4. Symbol VCC VI VO Tamb t/V Operating conditions Parameter supply voltage input voltage output voltage ambient temperature input transition rise and fall rate pin INH; VCC = 4.5 V Conditions Min 4.5 0 0 -40 1.67 Typ 5.0 Max 5.5 VCC VCC +125 139 Unit V V V C ns/V
11. Static characteristics
Table 5. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Tamb = 25 C Phase comparator section VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage pins SIG_IN and COMP_IN; VCC = 4.5 V; DC coupled pins SIG_IN and COMP_IN; VCC = 4.5 V; DC coupled pins PCP_OUT and PCn_OUT; VCC = 4.5 V; VI = VIH or VIL IO = -20 A IO = -4.0 mA VOL LOW-level output voltage pins PCP_OUT and PCn_OUT; VCC = 4.5 V; VI = VIH or VIL IO = 20 A IO = 4.0 mA II IOZ RI input leakage current OFF-state output current input resistance pins SIG_IN and COMP_IN; VCC = 5.5 V; VI = VCC or GND pin PC2_OUT; VCC = 5.5 V; VI = VIH or VIL; VO = VCC or GND SIG_IN and COMP_IN; VCC = 4.5 V; VI at self-bias operating point; VI = 0.5 V; see Figure 14, 15 and 16 Rbias Icp VCO section VIH VIL HIGH-level input voltage LOW-level input voltage pin INH; VCC = 4.5 V to 5.5 V; DC coupled pin INH; VCC = 4.5 V to 5.5 V; DC coupled 2.0 1.6 1.2 0.8 V V bias resistance charge pump current VCC = 4.5 V VCC = 4.5 V; Rbias = 40 k 25 250 k 0.53 1.06 2.12 mA 250 0.5 A k 0 0.15 0.1 0.26 30 V V A 4.4 3.98 4.5 4.32 V V 2.1 1.35 V 3.15 2.4 V Parameter Conditions Min Typ Max Unit
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74HCT9046A
PLL with band gap controlled VCO
Table 5. Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol VOH Parameter HIGH-level output voltage Conditions pin VCO_OUT; VCC = 4.5 V; VI = VIH or VIL IO = -20 A IO = -4.0 mA VOL LOW-level output voltage pin VCO_OUT; VCC = 4.5 V; VI = VIH or VIL IO = 20 A IO = 4.0 mA pins C1A and C1B; VCC = 4.5 V; VI = VIH or VIL; IO = 4.0 mA II R1 R2 C1 VVCO_IN input leakage current resistor 1 resistor 2 capacitor 1 voltage on pin VCO_IN pins INH and VCO_IN; VCC = 5.5 V; VI = VCC or GND VCC = 4.5 V VCC = 4.5 V VCC = 4.5 V over the range specified for R1 VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V Demodulator section Rs series resistance VCC = 4.5 V; at Rs > 300 k the leakage current can influence VDEM_OUT VCO_IN to VDEM_OUT; VCC = 4.5 V; VI = VVCO_IN = 0.5VCC; values taken over Rs range; see Figure 17 DEM_OUT; VCC = 4.5 V; VDEM_OUT = 0.5VCC disabled; VCC = 5.5 V; pin INH at VCC pin INH; VI = VCC - 2.1 V; VCC = 4.5 V; other inputs at VCC or GND; 50 300 k 1.1 1.1 1.1 3.4 3.9 4.4 V V V 3 3 40 0 0.15 0.1 0.26 0.40 0.1 300 300 no limit V V V A k k pF 4.4 3.98 4.5 4.32 V V Min Typ Max Unit
Voffset
offset voltage
-
20
-
mV
Rdyn General ICC ICC CI
dynamic resistance
-
25
-
supply current additional supply current input capacitance
-
100 3.5
8.0 360 -
A A pF
Tamb = -40 C to +85 C Phase comparator section VIH VIL HIGH-level input voltage LOW-level input voltage pins SIG_IN and COMP_IN; VCC = 4.5 V; DC coupled pins SIG_IN and COMP_IN; VCC = 4.5 V; DC coupled 1.35 V 3.15 V
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Product data sheet
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74HCT9046A
PLL with band gap controlled VCO
Table 5. Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol VOH Parameter HIGH-level output voltage Conditions pins PCP_OUT and PCn_OUT; VCC = 4.5 V; VI = VIH or VIL IO = -20 A IO = -4.0 mA VOL LOW-level output voltage pins PCP_OUT and PCn_OUT; VCC = 4.5 V; VI = VIH or VIL IO = 20 A IO = 4.0 mA II IOZ VCO section VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage pin INH; VCC = 4.5 V to 5.5 V; DC coupled pin INH; VCC = 4.5 V to 5.5 V; DC coupled pin VCO_OUT; VCC = 4.5 V; VI = VIH or VIL IO = -20 A IO = -4.0 mA VOL LOW-level output voltage pin VCO_OUT; VCC = 4.5 V; VI = VIH or VIL IO = 20 A IO = 4.0 mA pins C1A and C1B; VCC = 4.5 V; VI = VIH or VIL; IO = 4.0 mA II General ICC ICC supply current additional supply current disabled; VCC = 5.5 V; pin INH at VCC per input pin; VI = VCC - 2.1 V; VCC = 4.5 V; other inputs at VCC or GND; 80.0 450 A A input leakage current pins INH and VCO_IN; VCC = 5.5 V; VI = VCC or GND 0.1 0.33 0.47 1.0 V V V A 4.4 3.84 V V 2.0 0.8 V V input leakage current OFF-state output current SIG_IN and COMP_IN; VCC = 5.5 V; VI = VCC or GND PC2_OUT; VCC = 5.5 V; VI = VIH or VIL; VO = VCC or GND 5.0 A 0.1 0.33 38 V V A 4.4 3.84 V V Min Typ Max Unit
Tamb = -40 C to +125 C Phase comparator section VIH VIL HIGH-level input voltage LOW-level input voltage pins SIG_IN and COMP_IN; VCC = 4.5 V; DC coupled pins SIG_IN and COMP_IN; VCC = 4.5 V; DC coupled 1.35 V 3.15 V
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PLL with band gap controlled VCO
Table 5. Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol VOH Parameter HIGH-level output voltage Conditions pins PCP_OUT and PCn_OUT; VCC = 4.5 V; VI = VIH or VIL IO = -20 A IO = -4.0 mA VOL LOW-level output voltage pins PCP_OUT and PCn_OUT; VCC = 4.5 V; VI = VIH or VIL IO = 20 A IO = 4.0 mA II IOZ VCO section VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage pin INH; VCC = 4.5 V to 5.5 V; DC coupled pin INH; VCC = 4.5 V to 5.5 V; DC coupled pin VCO_OUT; VCC = 4.5 V; VI = VIH or VIL IO = -20 A IO = -4.0 mA VOL LOW-level output voltage pin VCO_OUT; VCC = 4.5 V; VI = VIH or VIL IO = 20 A IO = 4.0 mA pins C1A and C1B; VCC = 4.5 V; VI = VIH or VIL; IO = 4.0 mA II General ICC ICC supply current additional supply current disabled; VCC = 5.5 V; pin INH at VCC per input pin; VI = VCC - 2.1 V; VCC = 4.5 V; other inputs at VCC or GND; 160.0 A 490 A input leakage current pins INH and VCO_IN; VCC = 5.5 V; VCC or GND 0.1 0.4 0.54 1.0 V V V A 4.4 3.7 V V 2.0 0.8 V V input leakage current OFF-state output current pins SIG_IN and COMP_IN; VCC = 5.5 V; VI = VCC or GND pin PC2_OUT; VCC = 5.5 V; VI = VIH or VIL; VO = VCC or GND 10.0 A 0.1 0.4 45 V V A 4.4 3.7 V V Min Typ Max Unit
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74HCT9046A
PLL with band gap controlled VCO
mbd108
800 RI (k)
mga956 - 1
II
VI
600
400 VCC = 4.5 V 200 self-bias operating point 0 (0.5 VCC) - 0.25 0.5 VCC
5.5 V
VI (V) (0.5 VCC) + 0.25
VI
Fig 14. Typical input resistance curve at SIG_IN and COMP_IN
mga957
Fig 15. Input resistance at SIG_IN; COMP_IN with VI = 0.5 V at self-bias point
60 Voffset (mV) 40
mga958
5 VCC = 5.5V 4.5 V
II (A)
20 0 0 4.5 V 5.5 V -20 5.5 V VCC = 4.5 V
-5 (0.5 VCC) - 0.25
0.5 VCC
VI (V)
(0.5 VCC) + 0.25
-40 (0.5 VCC) - 2
0.5 VCC (0.5 VCC) + 2 VVCO_IN (V)
___ Rs = 50 k - - - Rs = 300 k
Fig 16. Input current at SIG_IN; COMP_IN with VI = 0.5 V at self-bias point
Fig 17. Offset voltage at demodulator output as a function of VCO_IN and Rs
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PLL with band gap controlled VCO
12. Dynamic characteristics
Table 6. Dynamic characteristics[1] GND = 0 V; tr = tf = 6 ns; CL = 50 pF. Symbol Tamb = 25 C Phase comparator section tpd propagation delay SIG_IN, COMP_IN to PC1_OUT; VCC = 4.5 V; see Figure 18 SIG_IN, COMP_IN to PCP_OUT; VCC = 4.5 V; see Figure 18 ten tdis tt Vi(p-p) VCO section f f0 frequency deviation center frequency VCC = 5.0 V; VVCO_IN = 3.9 V; R1 = 10 k; R2 = 10 k; C1 = 1 nF VCC = 4.5 V; duty cycle = 50 %; VVCO_IN = 0.5VCC; R1 = 4.3 k; R2 = ; C1 = 40 pF; see Figure 23 and 31 VCC = 5 V; duty cycle = 50 %; VVCO_IN = 0.5VCC; R1 = 3 k; R2 = ; C1 = 40 pF; see Figure 23 and 31 f/f General CPD power dissipation capacitance
[2][3] [5]
Parameter
Conditions
Min
Typ
Max
Unit
[4]
23 35 30 36 7 50
40 68 56 65 15 -
ns ns ns ns ns mV
enable time disable time transition time peak-to-peak input voltage
SIG_IN, COMP_IN to PC2_OUT; VCC = 4.5 V; see Figure 19 SIG_IN, COMP_IN to PC2_OUT; VCC = 4.5 V; see Figure 19 VCC = 4.5 V; see Figure 18 pin SIGN_IN or COMP_IN; VCC = 4.5 V; AC coupled; fi = 1 MHz
-
-10 11.0
15.0
+10 -
% MHz
-
16.0
-
MHz
relative frequency variation duty cycle
VCC = 4.5 V; R1 = 100 k; R2 = ; C1 = 100 pF; see Figure 24 and 25 VCO_OUT; VCC = 4.5 V
[6]
-
0.4 50 20
-
% % pF
Tamb = -40 C to +85 C Phase comparator section tpd propagation delay SIG_IN, COMP_IN to PC1_OUT; VCC = 4.5 V; see Figure 18 SIG_IN, COMP_IN to PCP_OUT; VCC = 4.5 V; see Figure 18 ten tdis tt VCO section enable time disable time transition time SIG_IN, COMP_IN to PC2_OUT; VCC = 4.5 V; see Figure 19 SIG_IN, COMP_IN to PC2_OUT; VCC = 4.5 V; see Figure 19 VCC = 4.5 V; see Figure 18 70 81 19 ns ns ns 85 ns 50 ns
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PLL with band gap controlled VCO
Table 6. Dynamic characteristics[1] ...continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF. Symbol f/T Parameter frequency variation with temperature Conditions VCC = 4.5 V; VVCO_IN = 0.5VCC; recommended range: R1 = 10 k; R2 = 10 k; C1 = 1 nF; see Figure 20, 21 and 22
[7]
Min -
Typ 0.06
Max -
Unit %/K
Tamb = -40 C to +125 C Phase comparator section tpd propagation delay SIG_IN, COMP_IN to PC1_OUT; VCC = 4.5 V; see Figure 18 SIG_IN, COMP_IN to PCP_OUT; VCC = 4.5 V; see Figure 18 ten tdis tt
[1] [2]
-
-
60 102 84 98 22
ns ns ns ns ns
enable time disable time transition time
SIG_IN, COMP_IN to PC2_OUT; VCC = 4.5 V; see Figure 19 SIG_IN, COMP_IN to PC2_OUT; VCC = 4.5 V; see Figure 19 VCC = 4.5 V; see Figure 18
tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH; tt is the same as tTLH and tTHL. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = total load switching outputs; (CL x VCC2 x fo) = sum of outputs. Applies to the phase comparator section only (pin INH = HIGH). For power dissipation of the VCO and demodulator sections, see Figure 26, 27 and 28. This is the (peak to peak) input sensitivity. This is the center frequency tolerance. This is the frequency linearity. This is the frequency stability with temperature change.
[3] [4] [5] [6] [7]
SIG_IN, COMP_IN inputs
VM
tPHL
tPLH
PCP_OUT, PC1_OUT outputs
VM
tTHL
tTLH
mbd106
VM = 0.5VCC; VI = GND to VCC.
Fig 18. Waveforms showing input (SIG_IN and COMP_IN) to output (PCP_OUT and PC1_OUT) propagation delays and the output transition times
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74HCT9046A
PLL with band gap controlled VCO
SIG_IN input
VM
COMP_IN input
VM tPHZ 90% tPLZ
tPZH PC2_OUT output
tPZL
VM 10%
mga941
VM = 0.5VCC; VI = GND to VCC.
Fig 19. Waveforms showing the enable and disable times for PC2_OUT
20 f (%) 10
mbd115
f (%)
15
mbd116
10
5
0
0
VCC = -10 5.5 V 4.5 V -20 -50 0 50 100 150 Tamb (C)
-5 -10
VCC = 5.5 V 4.5 V
-15 -50
0
50
100 150 Tamb (C)
a. R1 = 3 k; R2 = ; C1 = 100 pF.
b. R1 = 10 k; R2 = ; C1 = 100 pF.
Fig 20. Frequency stability of the VCO as a function of ambient temperature with supply voltage as a parameter
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74HCT9046A
PLL with band gap controlled VCO
10 f (%) 5
mbd124
VCC =
5.5 V 4.5 V
f (%)
15 10 5 0
mbd117
VCC =
0 -5 -5 -10 -15 -10 -50 -20 -50 5.5 V
4.5 V 0 50 100 150 Tamb (C)
0
50
100 150 Tamb (C)
a. R1 = 300 k; R2 = ; C1 = 100 pF.
b. R1 = ; R2 = 3 k; C1 = 100 pF.
Fig 21. Frequency stability of the VCO as a function of ambient temperature with supply voltage as a parameter
8 f (%) 4
mbd118
10 f (%) 5
mbd119
0 0 -4
VCC =
5.5 V -5
VCC =
4.5 V 5.5 V
-8 4.5 V -12 -50 0 50 100 150 Tamb (C)
-10 -50
0
50
100 150 Tamb (C)
a. R1 = ; R2 = 10 k; C1 = 100 pF.
b. R1 = ; R2 = 300 k; C1 = 100 pF.
Fig 22. Frequency stability of the VCO as a function of ambient temperature with supply voltage as a parameter
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74HCT9046A
PLL with band gap controlled VCO
30 fVCO (MHz) 20 VCC = 4.5 V 10 5.5 V
mbd112
30 fVCO (kHz) 20 VCC = 4.5 V
mbd113
5.5 V
10
0 0 2 4 VVCO_IN (V) 6
0 0 2 4 VVCO_IN (V) 6
a. R1 = 4.3 k; C1 = 39 pF.
mbd120
b.
R1 = 4.3 k; C1 = 100 nF.
mbd111
800 fVCO (kHz) 600 VCC = 5.5 V 4.5 V
400 f
VCO
(Hz) 300
VCC = 5.5 V frequency 4.5 V frequency
400
200
200
100
0 0 2 4 VVCO_IN (V) 6
0 0 2 4 VVCO_IN (V) 6
c. R1 = 300 k; C1 = 39 pF.
d. R1 = 300 k; C1 = 100 nF.
Fig 23. Graphs showing VCO frequency as a function of the VCO input voltage (VVCO_IN)
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74HCT9046A
PLL with band gap controlled VCO
4
mbd114
mga937
fVCO
(%) 0
C1 = 1 F 4.5 V 5.5 V
f (MHz) f2 f0 f' 0 f1
C1 = 39 pF 4.5 V
-4
V min 0.5 VCC
V max VVCO_IN (V) -8 1
5.5 V
10
10 2
3 R1 (k) 10
f1 + f2 f` 0 = ----------------2
linearity = ----------------- x 100 % -
R2 = and V = 0.5 V
f` 0 - f 0 f0
Fig 24. Definition of VCO frequency linearity: V = 0.5 V over the VCC range
mbd121
Fig 25. Frequency linearity as a function of R1, C1 and VCC
1
VCC =
5.5 V C1 = 39 pF 4.5 V C1 = 39 pF
mbd110
1
PD (W)
VCC = 5.5 V C1 = 1 F 4.5 V C1 = 1 F
PD
(W)
10 1
10
5.5 V C1 = 39 pF 4.5 V C1 = 39 pF
1
5.5 V 4.5 V C1 = 1 F
10 2
10
0 100 200 R1 (k) 300
2
0 R1 =
100
200
R2 (k)
300
R2 =
Fig 26. Power dissipation as a function of R1
Fig 27. Power dissipation as a function of R2
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PLL with band gap controlled VCO
10 3
mbd109
PDEM (W)
VCC =
10 4
4.5 V 5.5 V
10 5 10
102
Rs (k)
10 3
Fig 28. Typical power dissipation as a function of Rs
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74HCT9046A
PLL with band gap controlled VCO
13. Application information
This information is a guide for the approximation of values of external components to be used with the 74HCT9046A in a phase-locked-loop system. Values of the selected components should be within the ranges shown in Table 7.
Table 7. R1 R2 R1 + R2 C1 Table 8. Subject VCO frequency without extra offset Survey of components Value between 3 k and 300 k between 3 k and 300 k parallel value > 2.7 k > 40 pF Design considerations for VCO section Phase comparator PC1, PC2 Design consideration VCO frequency characteristic. With R2 = and R1 within the range 3 k < R1 < 300 k, the characteristics of the VCO operation will be as shown in Figure 29a. (Due to R1, C1 time constant a small offset remains when R2 = ). Selection of R1 and C1. Given f0, determine the values of R1 and C1 using Figure 31. Given fmax and f0 determine the values of R1 and C1 using Figure 31; use Figure 33 to obtain 2fL and then use this to calculate fmin. VCO frequency characteristic. With R1 and R2 within the ranges 3 k < R1 < 300 k < R2 < 300 k, the characteristics of the VCO operation is as shown in Figure 29b. Selection of R1, R2 and C1. Given f0 and fL determine the value of product R1C1 by using Figure 33. Calculate foff from the equation foff = f0 - 1.6fL. Obtain the values of C1 and R2 by using Figure 32. Calculate the value of R1 from the value of C1 and the product R1C1. VCO adjusts to f0 with PC_IN = 90 and VVCO_IN = 0.5VCC VCO adjusts to foffset with PC_IN = -360 and VVCO_IN = minimum
Component
PC1 PC2 VCO frequency with extra offset PC1, PC2
PC1, PC2
PLL conditions with no signal at pin SIG_IN
PC1 PC2
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74HCT9046A
PLL with band gap controlled VCO
mga938
f VCO
f max f0 f min 1.1 V 0.5 VCC VCC-1.1 V VCC 2f L due to R1,C1
VCO_IN
a. Operating without offset; f0 = center frequency; 2fL = frequency lock range.
mga939
f VCO
f max f0 f min f off 0.6fL due to R2,C1 2fL due to R1,C1
1.1 V
0.5 VCC
VCC-1.1 V
VCC
VCO_IN
b. Operating with offset; f0 = center frequency; 2fL = frequency lock range. Fig 29. Frequency characteristic of VCO
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74HCT9046A
PLL with band gap controlled VCO
13.1 Filter design considerations for PC1 and PC2 of the 74HCT9046A
Figure 30 shows some examples of passive and active filters to be used with the phase comparators of the 74HCT9046A. Transfer functions of phase comparators and filters are given in Table 9.
Table 9. Transfer functions of phase comparators and filters Explanation V CC K PC1 = ---------- V /r 1 = R3 x C2; 2 = R4 x C2; 3 = R4 x C3; A = 105 = DC gain amplitude PC2 5 K PC + ----- /r -V 4 Figure Figure 30a Filter type passive filter without damping passive filter with damping active filter with damping passive filter with damping Transfer function 1 F ( j ) = --------------------1 + j 1 1 + j 2 F ( j ) = ------------------------------------1 + j ( 1 + 2 ) 1 + j 2 1 + j 2 F ( j ) = --------------------------- --------------------1/ A + j 1 j 1 1 + j 2 1 + j 2 F ( j ) = ---------------------------- --------------------1 A + j 1 j 1 A = 105 = DC gain amplitude active filter with damping 1 + j 2 1 + j 2 F ( j ) = --------------------------- --------------------1/ A + j 1 j 1 A = 105 = DC gain amplitude
Phase comparator PC1
Figure 30b
Figure 30c
Figure 30d
1 = R3' x C2; 2 = R4 x C2; Figure 30e 3 = R4 x C3; R3' = Rbias/17; Rbias = 25 k to 250 k
Table 10. Subject
General design considerations Phase comparator PC1 PC2 PC1 PC2 PC1 PC2 Design consideration yes no high low fr = 2fi; large ripple content at PC_IN = 90 fr = fi; small ripple content at PC_IN = 0
PLL locks on harmonics at center frequency Noise rejection at signal input AC ripple content when PLL is locked
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74HCT9046A
PLL with band gap controlled VCO
PC1 CIRCUIT
F(j)
R3
AMPLITUDE CHARACTERISTIC
POLE ZERO DIAGRAM
C2
1/ 1
X 1/ 1
(a)
F(j)
R3
1/ 2
C3 R4
1/ 3 O 1/ 2 X 1
1/ 1 2
C2
1 2
(b)
A
C3 C2 R4 R3
1/ 2
1/ 3 O 1/ 2 X 1/ A 1
1/ A 1 A
(c)
PC2
A
R3'
1/ 2
R4
1/ 3 O 1/ 2 X 1/ A 1
AR3' C2
1/A 1
(d)
A
C3 C2 R4 R3'
1/ 2
1/ 3 O 1/ 2 X 1/ A 1
A
1/A 1
(e)
mbd107
Fig 30. Passive and active filters for 74HCT9046A
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74HCT9046A
PLL with band gap controlled VCO
108 f0 (Hz) 107 106 105 104 103 102 10 1 10 102 103 104 105
mbd103
(1) (2) (3) (4) (5) (6) (7) (8)
106 107 C1 (pF)
VCC = 5.5 V; R1 = 3 k. VCC = 4.5 V; R1 = 3 k. VCC = 5.5 V; R1 = 10 k. VCC = 4.5 V; R1 = 10 k. VCC = 5.5 V; R1 = 150 k. VCC = 4.5 V; R1 = 150 k. VCC = 5.5 V; R1 = 300 k. VCC = 4.5 V; R1 = 300 k. R2 = ; VVCO_IN = 0.5VCC; INH = GND; Tamb = 25 C.
Fig 31. Typical value of VCO center frequency (f0) as a function of C1
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PLL with band gap controlled VCO
108 foff (Hz) 107 106 105 104 103 102 10 1 10 102 103 104 105
mbd104
(1) (2)
(3) (4)
106 107 C1 (pF)
VCC = 4.5 V to 5.5 V; R1 = 3 k. VCC = 4.5 V to 5.5 V; R1 = 10 k. VCC = 4.5 V to 5.5 V; R1 = 150 k. VCC = 4.5 V to 5.5 V; R1 = 300 k. R1 = ; VVCO_IN = 0.5VCC; INH = GND; Tamb = 25 C.
Fig 32. Typical value of frequency offset as a function of C1
108 2fL (Hz) 107 106 105 104 103 102 10 10-7
mbd105
VCC = 5.5 V 4.5 V 10-6 10-5 10-4 10-3 10-2 10-1 1 R1C1 (s)
2fL K v = --------------------------------------- 2 ( r s V ) V VCO_IN range
VVCO_IN = 1.1 V to (VCC - 1.1) V
Fig 33. Typical frequency lock range 2fL as a function of the product R1 and C1
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PLL with band gap controlled VCO
13.2 PLL design example
The frequency synthesizer used in the design example shown in Figure 34 has the following parameters: Output frequency: 2 MHz to 3 MHz Frequency steps: 100 kHz Settling time: 1 ms Overshoot: < 20 % The open loop gain is: H (s) x G(s) = K p x K f x K o x K n and the closed loop: K p x K f x Ko x Kn u ------ = ------------------------------------------------------1 + K p x K f x Ko x Kn i where: Kp = phase comparator gain Kf = low-pass filter transfer gain Ko = Kv/s VCO gain Kn = 1n divider ratio The programmable counter ratio Kn can be found as follows: f OUT 2 MHz N min = ------------ = -------------------- = 20 100 kHz f step f OUT 3 MHz N max = ------------ = -------------------- = 30 f step 100 kHz The VCO is set by the values of R1, R2 and C1; R2 = 10 k (adjustable). The values can be determined using the information in Table 8. With f0 = 2.5 MHz and fL = 500 kHz this gives the following values (VCC = 5.0 V): R1 = 30 k R2 = 30 k C1 = 100 pF The VCO gain is: 2 f L x 2 1 MHz 6 K v = ----------------------------------------- = ---------------- x 2 2.24 x 10 r s V 2.8 ( V CC - 1.1 ) - 1.1 The gain of the phase comparator PC2 is:
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PLL with band gap controlled VCO
5 K p = ----------- = 0.4 V r 4x Using PC2 with the passive filter as shown in Figure 34 results in a high gain loop with the same performance as a loop with an active filter. Hence loop filter equations as for a high gain loop should be used. The current source output of PC2 can be simulated then with a fictive filter resistance: R bias R3` = ----------17 The transfer functions of the filter is given by: 1 + s 2 K f = ---------------s 2 Where: 1 = R3` x C2 2 = R4 x C2 The characteristic equation is: 1 + K p x K f x K o x K n This results in: 1 + s 2 K v 1 + K p ---------------- ----- K n = 0 s 1 - sor: 2 2 s + sK p K v K n ---- + K p K v K n 1 = 0 1 This can be written as: s + 2 n s + ( n ) = 0 with the natural frequency n defined as: n = K p x Kv x Kn -------------------------------1
2 2
and the damping value given as: = 0.5 x 2 x n In Figure 35 the output frequency response to a step of input frequency is shown. The overshoot and settling time percentages are now used to determine n. From Figure 35 it can be seen that the damping ratio = 0.707 will produce an overshoot of less than 20 % and settle to within 5 % at nt = 5. The required settling time is 1 ms. This results in:
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PLL with band gap controlled VCO
3 5 5 n = -- = ------------ = 5 x 10 r s t 0.001
Rewriting the equation for natural frequency results in: K p x Kv x Kn 1 = -------------------------------2 ( n ) The maximum overshoot occurs at Nmax = 30; hence Kn = 130: 0.4 x 2.24 x 10 1 = -------------------------------------- = 0.0012 2 5000 x 30 When C2 = 470 nF, it follows: 1 0.0012 R3` = ------ = ------------------------- = 2550 -9 C2 470 x 10 Hence the current source bias resistance R bias = 17 x 2550 = 43 k With = 0.707 (0.5 x 2 x n) it follows: 0.707 2 = ------------------------- = 0.00028 0.5 x 5000 2 0.00028 R4 = ------ = ------------------------- = 600 -9 C2 470 x 10 For extra ripple suppression a capacitor C3 can be connected in parallel with R4, with an extra 3 = R4 x C3. For stability reasons 3 should be < 0.12, hence C3 < 0.1C2 or C3 = 39 nF.
6
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NXP Semiconductors
74HCT9046A
PLL with band gap controlled VCO
Kp 100 kHz OSCILLATOR "HCU04" DIVIDE BY 10 "190" 14 3 PHASE COMPARATOR PC2
R3' (1)
Kf 13
R4 C3 C2 R1
Ko 9 4 fOUT
VCO 11
R2 C1
15
12 6
7
5
u
1 MHz
Kn PROGRAMMABLE DIVIDER "4059"
Rbias
mbd098
(1) R3' = fictive resistance R3' = -----------C1 = 100 pF C2 = 470 nF C3 = 39 nF R1 = 30 k R2 = 30 k R3' = 2550 Rbias = 43 k R4 = 600
R bias 17
Fig 34. Frequency synthesizer
1.6
mga959
-0.6 -0.4 -0.2
e(t) e/n
1.4
= 0.3
0.5 0.707 1.0
e(t) e/n
1.2
= 5.0
1.0
= 2.0
0
0.8
0.2
0.6
0.4
0.4
0.6
0.2
0.8
0
0
1
2
3
4
5
6
7
nt
8
1.0
Fig 35. Type 2, second order frequency step response
74HCT9046A_6
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 -- 15 September 2009
36 of 43
NXP Semiconductors
74HCT9046A
PLL with band gap controlled VCO
3.1 proportional to output frequency (MHz) 2.9 step input 2.1 N stepped from 21 to 20 2.0 N = 30
mga952
N stepped from 29 to 30
1.9
0
0.5
1.0
1.5
2.0 2.5 time (ms)
Fig 36. Frequency compared to the time response
Since the output frequency is proportional to the VCO control voltage, the PLL frequency response can be observed with an oscilloscope by monitoring pin VCO_IN of the VCO. The average frequency response, as calculated by the Laplace method, is found experimentally by smoothing this voltage at pin VCO_IN with a simple RC filter, whose time constant is long compared with the phase detector sampling rate but short compared with the PLL response time.
13.3 Further information
For an extensive description and application example please refer to "Application note" ordering number 9397 750 00078.
74HCT9046A_6
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 -- 15 September 2009
37 of 43
NXP Semiconductors
74HCT9046A
PLL with band gap controlled VCO
14. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4
D seating plane
ME
A2
A
L
A1
c Z e b1 b 16 9 b2 MH wM (e 1)
pin 1 index E
1
8
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 b2 1.25 0.85 0.049 0.033 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 0.76 0.03
Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT38-4 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION
ISSUE DATE 95-01-14 03-02-13
Fig 37. Package outline SOT38-4 (DIP16)
74HCT9046A_6 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 -- 15 September 2009
38 of 43
NXP Semiconductors
74HCT9046A
PLL with band gap controlled VCO
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A X
c y HE vMA
Z 16 9
Q A2 pin 1 index Lp 1 e bp 8 wM L detail X A1 (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3
0.010 0.057 0.069 0.004 0.049
0.019 0.0100 0.39 0.014 0.0075 0.38
0.244 0.041 0.228
0.028 0.004 0.012
8 o 0
o
ISSUE DATE 99-12-27 03-02-19
Fig 38. Package outline SOT109-1 (SO16)
74HCT9046A_6 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 -- 15 September 2009
39 of 43
NXP Semiconductors
74HCT9046A
PLL with band gap controlled VCO
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c y HE vMA
Z
16
9
Q A2 pin 1 index A1 Lp L (A 3) A
1
e bp
8
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18
Fig 39. Package outline SOT403-1 (TSSOP16)
74HCT9046A_6 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 -- 15 September 2009
40 of 43
NXP Semiconductors
74HCT9046A
PLL with band gap controlled VCO
15. Abbreviations
Table 11. Acronym CMOS DUT ESD HBM MM PLL VCO Abbreviations Description Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Phase Locked Loop Voltage Controlled Oscillator
16. Revision history
Table 12. Revision history Release date 20090915 Data sheet status Product data sheet Change notice Supersedes 74HCT9046A_5 Document ID 74HCT9046A_6 Modifications:
* * * * *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Vi(p-p) value changed from 15 mV to 50 mV in Section 12. f/T value moved from minimum to typical column Section 12. Package version SOT38-1 changed to SOT38-4 in Section 4 and Figure 37. Product specification Product specification Product specification 74HCT9046A_4 74HCT9046A_3 -
74HCT9046A_5 74HCT9046A_4 74HCT9046A_3
20031030 20030515 19990111
74HCT9046A_6
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 -- 15 September 2009
41 of 43
NXP Semiconductors
74HCT9046A
PLL with band gap controlled VCO
17. Legal information
17.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
17.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
18. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
74HCT9046A_6
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 -- 15 September 2009
42 of 43
NXP Semiconductors
74HCT9046A
PLL with band gap controlled VCO
19. Contents
1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.3.1 8.3.2 8.4 9 10 11 12 13 13.1 13.2 13.3 14 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Differences with respect to the familiar 74HCT4046A . . . . . . . . . . . . . . . . . . . . . . . . . . 6 VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Phase comparators. . . . . . . . . . . . . . . . . . . . . . 7 Phase Comparator 1 (PC1) . . . . . . . . . . . . . . . 7 Phase Comparator 2 (PC2) . . . . . . . . . . . . . . . 9 Loop filter component selection . . . . . . . . . . . 13 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14 Recommended operating conditions. . . . . . . 15 Static characteristics. . . . . . . . . . . . . . . . . . . . 15 Dynamic characteristics . . . . . . . . . . . . . . . . . 20 Application information. . . . . . . . . . . . . . . . . . 27 Filter design considerations for PC1 and PC2 of the 74HCT9046A . . . . . . . . . . . . . . . . 29 PLL design example . . . . . . . . . . . . . . . . . . . . 33 Further information . . . . . . . . . . . . . . . . . . . . . 37 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 38 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 41 Legal information. . . . . . . . . . . . . . . . . . . . . . . 42 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 42 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Contact information. . . . . . . . . . . . . . . . . . . . . 42 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 15 September 2009 Document identifier: 74HCT9046A_6

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